The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with burst access mode.
A computer main memory device performs input/output operations for inputting and outputting a column of data with continuous address for cache memory in synchronizing with reference clock signals having externally entered. This data transmission is so called as burst transmission. A length of data column to be inputted or outputted in correspondence with a single designated address is so called to be burst length. A synchronous dynamic random access memory device is one of the typical memory devices which exhibit burst transmissions.
FIG. 1 is a block diagram illustrative of a conventional synchronous dynamic random access memory. FIG. 2 is a timing chart of the conventional synchronous dynamic random access memory shown in FIG. 1. Upon input of read/write commands into a command decoder 30, an external address is transmitted from the command decoder 30 into a burst counter 31, so that, in accordance with both a burst length signal having already set therein and the fetched external address signal, a single internal address is generated by the burst counter 31. Subsequently, this generated single internal address is sent from the burst counter 31 to a multi-bit pre-fetch address generator circuit 32, so that the multi-bit pre-fetch address generator circuit 32 generates plural internal addresses in accordance with the single internal address. Those plural internal addresses are individually sent from the multi-bit pre-fetch address generator circuit 32 to a plurality of internal address driver circuits 34 and 35. The individual internal address driver circuits 34 and 35 are connected to corresponding plural memory cell arrays 36 and 37. For example, the internal address driver circuit 34 is connected to the memory cell array 36, and the internal address driver circuit 35 is connected to the memory cell array 37, so that the individual memory cell arrays 36 and 37 are separately driven in data input/output operations by the corresponding internal address driver circuits 34 and 35. Thereafter, during a time period of predetermined number cycles, the burst counter 31 remains operated to generate fresh internal addresses so that the data input/output operations to the plural memory cell arrays are successively conducted.
Recently, the requirement for further increase in operational speed of the synchronous dynamic random access memory has been on the increase. The above conventional synchronous dynamic random access memory has the limit of its high speed performance. After the read/write commands have been processed by the burst counter 31 to have generated the single internal address, then the multi-bit pre-fetch address generator circuit 32 receives the single internal address from the burst counter 31 and generate plural internal addresses for multi-bit pre-fetch operations before the individual internal address driver circuits 34 and 35 receive the corresponding internal addresses for individually and separately driving the corresponding memory cell arrays 36 and 37. This those purposes, the multi-bit pre-fetch address generator circuit 32 is connected between the burst counter 31 and the plural internal address driver circuits 34 and 35. This conventional circuit configuration causes a reduction in read/write operation speed of the synchronous dynamic random access memory. Namely, an access path of the conventional circuit configuration is so long as causing reduction in read/write operation speed because the access path has many circuit elements, for example, command latches 38, the command decoder 30, the burst counter 31, the multi-bit pre-fetch address generator circuit 32, the internal address driver circuits 34 and 35, and the memory cell arrays 36 and 37.
In the above circumstances, it had been required to develop a novel semiconductor memory device with the burst access mode and the multi-bit pre-fetch operations free from the above problem.